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CI Plus
The CI Plus library provides a programmable bi-directional I/O cell designed to meet the signal interface requirements of the Common Interface. This library is offered as a supplement to the I/O
libraries provided by Aragio Solutions. This library is compatible with the CI Plus Specification, but it is not fully compliant. The I/O cell is 5V
tolerant and interfaces to the Common Interface at TTL logic levels, but operates in the 3.3V power domain.
libraries provided by Aragio Solutions. This library is compatible with the CI Plus Specification, but it is not fully compliant. The I/O cell is 5V
tolerant and interfaces to the Common Interface at TTL logic levels, but operates in the 3.3V power domain.
Features
- • High performance, programmable general purpose I/O cells
- o 5V tolerant @ 3.3V operation
- o CI Plus compatible
- • Staggered CUP wire bond implementation with flip chip option
- • Power supply sequencing independent design with Power-On Control
- • Robust ESD Protection
- 2KV ESD Human Body Model (HBM)
- ▪ Compliant with JEDEC specification JS-001-2012 (April 2012)
- 200 V ESD Machine Model (MM)
- ▪ Compliant with JEDEC specification JESD22-A115C (November 2010)
- 500 V ESD Charge Device Model (CDM)
- ▪ Compliant with JESD22-C101E (December 2009)
- • Latch-up Immunity
- Compliant with JESD78D (November 2011)
- Tested using I-Test criteria of ±100mA at maximum ambient temperature of +125°C.
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
View CI Plus full description to...
- see the entire CI Plus datasheet
- get in contact with CI Plus Supplier
GPIO IP
- APB4 General Purpose Input/Output Module
- A 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- A 16nm/12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain, 5V OTP and 1.8V / 3.3V analog
- A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
- A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell
- A 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF