English
You are here:
Clock/Data Recovery PLL
The MXLCDR is a clock/data recovery PLL implemented using a digital CMOS process. It is highly integrated and require no external components. Differential circuit techniques are employed to attain low jitter in the noisy environment typical of multi-million gates digital chip.
The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
Features
- High performance, clock and data recovery PLL
- Digital CMOS processes
- Low power dissipation
- No external components required
- High frequency, low jitter output
- Modular design to facilitate customization and process migration
- Performance is superior to that obtained using over sampling techniques
Deliverables
- Data Sheet
- GDSII
- LVS Netlist
- Integration Guidelines
- Timing Model
- Behavioral Model
- LEF File for P&R
View Clock/Data Recovery PLL full description to...
- see the entire Clock/Data Recovery PLL datasheet
- get in contact with Clock/Data Recovery PLL Supplier
CDR IP
- SONET/SDH OC-3 / OC-12 Transceiver/CDR PHY
- Deserializer 1:32 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
- Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain
- Fractional N PLL 8.5-11.3GHz
- Dual Band 25.78125G/28Gbps SerDes/CDR Available in TSMC 28nm 9LM HPC+
- 2.5 Gbps Transceiver core