The MXLCDR is a clock/data recovery PLL implemented using a digital CMOS process. It is highly integrated and require no external components. Differential circuit techniques are employed to attain low jitter in the noisy environment typical of multi-million gates digital chip.
The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
- High performance, clock and data recovery PLL
- Digital CMOS processes
- Low power dissipation
- No external components required
- High frequency, low jitter output
- Modular design to facilitate customization and process migration
- Performance is superior to that obtained using over sampling techniques
- Data Sheet
- LVS Netlist
- Integration Guidelines
- Timing Model
- Behavioral Model
- LEF File for P&R