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Clock-Reset Generator
Features
- up to 16 programmable dividers
- dividers can change ratio "on-the fly"
- each divider provides up to 16 gated clocks and 1 ungated
- PLL software control - restart for changing frequency, stop mode, bypass mode
- input reset sources - external hardware reset and up to 16 reset requests from other devices
- output reset signals - 1 non-programmable and up to 32 programmable
- APB slave interface with internal asynchronous bridge for registers programming
- static RTL configurable options - number of dividers, width of dividers counters, aligning of clocks from different dividers, number of gated clocks for each divider, and others
View Clock-Reset Generator full description to...
- see the entire Clock-Reset Generator datasheet
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clock IP
- TSMC CLN7FF 7nm Clock Generator PLL - 800MHz-4000MHz
- TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz
- DLL (DDRs, Clock Domain Crossing, IO Deskewing)
- Real-Time-Clock with calendar, timer and alarm functions.
- Differential Receiver - TSMC 7FF
- Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock