The Clocking Wizard is provided under the terms of the Xilinx End User License and is included with ISE and Vivado software at no additional charge.
The Clocking Wizard simplifies the process of configuring the clocking resources in Xilinx FPGAs.
The LogiCORE™ IP Clocking Wizard generates HDL source code to configure a clock circuit to user requirements. The wizard can either automatically select an appropriate clocking primitive and configure buffering, feedback, and timing parameters for a clocking network, or help the user configure the attributes for a manually selected primitive. If desired, the user may also override any wizard-calculated parameter. Besides generating source HDL for the clocking circuit, the wizard also invokes the Xilinx timing analysis tools to generate a timing parameter report.
- Accepts up to two input clocks and up to seven output clocks per clock network
- Automatically chooses the correct clocking primitive for a selected device and configures the clocking primitive based on user-selected clocking features
- Calculates VCO frequency for primitives with an oscillator, and provides multiply and divide values based on input and output frequency requirements
- Implements an overall configuration that supports phase shift and duty cycle requirements
- Provides the ability to override an auto-selected clock primitive as well as any calculated attribute
- Provides spread spectrum clocking support
- Optionally buffers clock signals
- Provides timing estimates for the clock circuit as well as parameters that can be input into the Xilinx Power Estimator (XPE) for power consumption calculations