CML RapidIO SerDes

The use of Rapid IO supporting IP cores speeds the design cycle, increases design quality and allows greater degree of innovation, enabling companies to reduce design costs and create market differentiation. Although this IP is designed to be used with SRIO 2.1 HIP3100 IP core (developed by HDL Design House), it can be used by any digital interface which satisfies timing parameters. The HIPA 21000 is qualified to operate in industrial temperature range (-40°C to 85°C). In order to save power in case of no data transfer, the device can be driven in power down mode. Serial data transfer rate is to be chosen between five different values: 1.25Gbaud/s, 2.5Gbaud/s, 3.125Gbaud/s, 5Gbaud/s, 6.25Gbaud/s.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.

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