High-speed sense amplifier should be necessary with the low consumption power in readout the column A/D converter data of the CMOS image sensor (CIS). This sense amplifier gives major impact to the whole consumption power of the chip.
- Power Voltage : 1.2V< (CMOS switch is possible for power range)
- Readout Rate : 250MHz< (Current consumption, Devices dependence)
- Current Consumption : 50uA (Readout-rate, Bit-line parasitic CAP(Cp) dependence)
- Delay Time : 2nsec (Cp=2pF), 3nsec (Cp=4pF) (exclude effect of wire resistance)
- Control of timing is easy because pre-charge is unnecessary by the current detection type.
- Low power consumption is possible because it has only to be settling during 1 select.
- CMOS inverter composition is used as the first stage amplifier, and high-speed and low power consumption is realized.
- Offset cancel operation is done in blanking period, and faulty operation due to the element dispersion is prevented.
- This IP can use 90nm device low voltage of 1V.
- This IP can use Sinle-Slope column A/D converter.
- This IP can decrease very small consumption current.
- We uninvested form VC and other company now, so our IP can be very cheep.
- Our ASIC partner is GUC, PGC, Faraday, GSI.
- We can make Custom-CIS of used this IP.
- We are supplying circuits-macro for other IP license. And the customer can make hard-macro from circuits-macro.
- GDSII data
- SPICE netlist for LVS
- Timing models
- LEF file
- Verilog model
- Final simulation result
- Layout layer map file
- LVS and DRC log files
- Circuits data
- Simulation enviloment files
- IBIS or Hspice netlist file