The CI00201IP is CMOS Image Sensor A/D Convertor of Column/Parallel readout format. Speeding up and High resolution It can speed up and higher resolution by use of our “W-SA (Double Successive Approximation)”algorithm. It can decrease fixing pattern noise by use of Digital CDS between column to column.
- Power Voltage: 3V Analog 1.8V(1.2V) Analog/Digital Power Supply
- Input Clock: 25MHz
- A/D format: CURIOUS W-SA Format (Double Successive Approximation)
- A/D resolution: 12-bit (Full 13bit, 1bit margin for Digital CDS)
- A/D Conversion Time: 5uSec(3.75uSec)/Column(max)
- Power Consumption: 15uW / Column Circuit
- Column Pitch: 2.8uum/Column×2= 5.6um (2-Column perform sequential by 1-ADC)
- ADC Size (Length): 1.0mm
- Noise Reduction : Digital CDS
- This IP is used in Asian CIS(CMOS Image Sensor) LSI.
- This W-SA technology is our original.
- HDTV 12bit/60fps/2Mpixel and 2K4K more be available.
- This IP can add our Intarface IP(MIPI-DPHY,sub-LVDS,etc).
- We uninvested form VC and other company now, so our IP can be very cheep.
- Our ASIC partner is GUC, PGC, Faraday, GSI.
- We can make Custom-IP or Custom-CIS of used this IP.
- We are supplying circuits-macro for other IP license. And the customer can make hard-macro from circuits-macro.
- GDSII data
- SPICE netlist for LVS
- Timing models
- LEF file
- Verilog model
- Final simulation result
- Layout layer map file
- LVS and DRC log files
- Circuits data
- Simulation enviloment files
- IBIS or Hspice netlist file