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Voltage Monitor with Digital Output TSMC N5P (Multi-domain supply monitoring)
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ColdFire V2 SPPC1 Processor Platform (70011)
Building upon the 68K foundation, ColdFire offers RISC performance with industry-leading code density and a rich set of connectivity peripherals. By supporting variable-length instructions (16-, 32- or 48-bits long), the ColdFire Architecture enables higher code density than traditional 32- and 64-bit RISC machines. More efficient use of on-chip memory reduces bus bandwidth and external memory requirements, resulting in lower system cost.
The ColdFire Architecture is ubiquitous in consumer and industrial applications, which means a massive base of existing application code. ColdFire controllers continue to set the pace for the embedded market—from industrial automation systems to inkjet printers and media players.
The V2 ColdFire SPP takes you a step further toward building a complete SoC by integrating popular peripherals from Freescale’s Standard Product Platform with the V2 ColdFire Core, providing a full ColdFire-based subsystem. The peripheral set in the V2 ColdFire SPP is identical to that proven in Freescale’s MCF5208 devices.
The ColdFire Architecture is ubiquitous in consumer and industrial applications, which means a massive base of existing application code. ColdFire controllers continue to set the pace for the embedded market—from industrial automation systems to inkjet printers and media players.
The V2 ColdFire SPP takes you a step further toward building a complete SoC by integrating popular peripherals from Freescale’s Standard Product Platform with the V2 ColdFire Core, providing a full ColdFire-based subsystem. The peripheral set in the V2 ColdFire SPP is identical to that proven in Freescale’s MCF5208 devices.
Features
- Multi-AHB crossbar switch (AXBS) connects multiple masters with various slave IP blocks
- External Bus Interface for glueless connection to external memory devices
- 10/100 Fast Ethernet Controller (FEC) with direct memory access (DMA)
- Queued serial peripheral interface (QSPI)
- Full-duplex, 3-wire synchronous transfers
- Master mode operation with programmable bit rates
- I2C
- Three UARTs
- eDMA controller
- Four 32-bit timers
- Control module with software watchdog timer, wakeup control, reset status register, clock disable control for peripherals
Deliverables
- Verilog source code
- Integration Testbench and Test-suite
- Comprehensive Documentation
- Scripts for simulation and synthesis with support for common EDA tools
Block Diagram of the ColdFire V2 SPPC1 Processor Platform (70011) IP Core
Video Demo of the ColdFire V2 SPPC1 Processor Platform (70011) IP Core
View ColdFire V2 SPPC1 Processor Platform (70011) full description to...
- see the entire ColdFire V2 SPPC1 Processor Platform (70011) datasheet
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