This document provides technical information about the Lattice Common Public Radio Interface (CPRI) IP core. This IP core together with SERDES and Physical Coding Sublayer (PCS) functionality integrated in the LatticeECP3™ and ECP5™ LFE5UM FPGAs implements the physical layer of the CPRI specification and interleaves IQ data with synchronization, control and management information. It can be used to connect Radio Equipment Control (REC) and Radio Equipment (RE) modules.
The CPRI IP core implements not only all of the capabilities required to support the physical layer of the CPRI specification (basic function), but also specific requirements related to link delay accuracy (low latency character).
One CPRI core configuration for 5G version (4.9152 Gbps) is also supported. It is similar to the "low latency" one for 3G version except the data rate.