PT13 is a microprocessor IP core intended for simple control applications. It has a compact but efficient instruction set and is designed to use internal ASIC/CPLD/FPGA memory for both program and data storage making it a very cost effective solution for embedded control applications.
An editor and assembler are provided for efficient generation of machine code.
The intellectual property block is provided as RTL compliant Verilog-2001 source code for FPGAs from all vendors or for ASICs.
To reduce the logic cell count for the IP core each instruction is designed to take the same number of clock cycles, 16, regardless of the addressing mode used. Therefore the execution time of each instruction with, for example, a 27MHz clock is 1.6875MHz, or 0.59μs/instruction.
After a reset the internal state machines are reset and the Program counter (PC) is cleared. The program counter is then used to address the program memory, starting at address $0000. The data at that first location is then decoded by the Op-code decode block which, in turn, controls the sequencing of the control unit. Each machine cycle of the processor takes 16 input clock cycles and is sub-divided into Fetch, Decode, Execute andWrite-Back cycles.
If the Op-code is a branch instruction the branch address is read from the subsequent bytes of the ROM and replaces the PC contents to form the new address. Three stack pointer registers (SP) allows up to 3 program counter contents to be stored permitting a maximum of 3 nested sub routines to be called, (note: no RAM is needed for subroutine calls but only the program counter contents are stored).
Data is read from the RAM using an address formed by the lower 4 bits of a data page register and by an 8-bit offset which is part of the instruction. Data is written to the RAM using the same addressing method. The RAM address space is also used to connect peripheral devices.
This direct method of addressing may also be used to read data from the ROM, but with an extended address range using 6 bits of the data page register. The ROM contents may also be read using indexed addressing instructions where the lower byte is the content of Accumulator B. This is useful for reading data from tables for example.
PT13 has two accumulators, either of which may be operated on for all instructions save for the indexed addressing mode. Both accumulators have two status flags which are used for conditional branch instructions; zero which indicates the contents of the corresponding accumulator are $00 and which is valid for all instructions, and carry, which is used in arithmetic instructions and also for arithmetic shift and rotate instructions.
Block Diagram of the Compact 8-bit Microprocessor IP Core