Compact and Performance Efficiency 32-bit RISC-V Core

The AndesCore™ N225 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications with small gate count, and some dual-issue ability. In addition to commonly used RISC-V IMAC it supports the recently ratified ISA extensions such as B (bit manipulation) and Zce (code size reduction). The N225 implements ePMP to improve core security; and Andes V5 extensions that includes StackSafe™ (for hardware stack protection), CoDense™, PowerBrake and WFI/WFE. The N225 supports both four-wire and two-wire JTAG debug and instruction trace interface for software development. On the performance front, it deploys several configurable options such as dynamic branch prediction, local memories, multiplier optimized for performance or area. Instruction cache or read-only data access is supported with an external cache controller. Moreover, it comes with rich features to ease SoC integration such as CLIC and PLIC for interrupt handling; an AHB-Lite system bus and an AHB-lite low-latency interface; an APB bus for CPU local peripherals, and an AHB-Lite local memory access port for external bus masters.

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