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Compact, efficient 64-bit RISC-V processor with 5-stage pipeline
The H50 is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large address space. The core has a 5-stage pipeline and is offered in two versions.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the H50 and to generate corresponding hardware and software development kits.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the H50 and to generate corresponding hardware and software development kits.
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Block Diagram of the Compact, efficient 64-bit RISC-V processor with 5-stage pipeline
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