MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
Compact High-Speed 32-bit CPU Core with Level-2 Cache
A27L2 features branch prediction, level-1 instruction and data caches, level-2 unified cache, local memories, ECC error protection, and Andes Custom Extension™ to add custom instructions to accelerate performance and reduce power consumption. In addition, it incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. A27L2 also includes vectored and preemptive interrupt controller to serve diversified system events, AXI 128-bit bus, rich power management, and JTAG debug interface and trace interface for software development support.
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