English
You are here:
Compact High-Speed 64-bit CPU Core
AndesCore™ NX25F is a compact 64-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is tailored for high-performance embedded applications that needs to access address space over 4GB. NX25F also supports single- and double-precision floating point instructions. NX25F comes with options, including branch prediction for efficient branch execution, Instruction and Data caches, Local Memories for low-latency accesses, ECC for L1 memory soft error protection, and Andes Custom Extension™ (ACE) to add proprietary instructions to accelerate performance/power consumption critical spots.
NX25F's 5-stage pipeline is optimized for high operating frequency and high performance. Features also includes PLIC and vectored interrupts for serving various types of system events, AXI or AHB 64-bit data bus for addressing up to 64-bit address, PowerBrake, QuickNap™ and WFI mode for low power and power management, and JTAG debug interface for development support.
NX25F's 5-stage pipeline is optimized for high operating frequency and high performance. Features also includes PLIC and vectored interrupts for serving various types of system events, AXI or AHB 64-bit data bus for addressing up to 64-bit address, PowerBrake, QuickNap™ and WFI mode for low power and power management, and JTAG debug interface for development support.
View Compact High-Speed 64-bit CPU Core full description to...
- see the entire Compact High-Speed 64-bit CPU Core datasheet
- get in contact with Compact High-Speed 64-bit CPU Core Supplier
Block Diagram of the Compact High-Speed 64-bit CPU Core IP Core
64-bit CPU IP
- RISC-V Processor - RV12 - 32/64 bit, Single Core CPU
- Compact High-Speed 64-bit CPU for Real-time and Linux Applications
- 64-bit CPU with Modern RISC Architecture, MemBoost and PMA
- 64-bit embedded processor, fully compliant with the RISC-V ISA
- 64-bit CPU Core with Level-2 Cache Controller
- Mid-range, feature-rich 64-bit MIPS CPU