The 3GPP LTE FEC Encoder IP Core addresses the implementation of the FEC building blocks compliant to 3GPP TS 36.212 V 10.5.0. Specifically, the IP core offers an efficient, easy to customize and reliable implementation of the following blocks. Optimization techniques have been used to achieve a reduced cycle count in the design of key building blocks thus making it amenable to parallel implementation for increased data rate requirements of the order of few gigabits as demanded by futuristic implementations.
- Controlled selection of Turbo or Convolution path (based on data blocks input or control data input)
- Rate 1/3 tail biting Convolution encoder
- Rate 1/3 turbo encoder
- Rate matching for Turbo coded transport channels
- Rate matching for Convolution coded transport channels and control information
- Bit collection, selection and transmission.
- LTE/ LTE Advanced (LTE A) Complaint.
- Implements Turbo encoder as defined in Section 126.96.36.199 of the specification.
- Configurable Interleaver block sizes - Supports all block sizes i.e., K=40 – 6144 as defined in  for Turbo and small block lengths (Ex: up to 64) for Convolution.
- Default code rate achieved is 1/3 with rate matching for other code rates supported.
- Easy interface definition.
- Customization to AXI or Avalon bus interface supported.
- Bit accurate C and MATLAB models available for RTL test vector generation.
- Efficient design and easily customizable to suit different standards or polynomial definitions.
- Licensable in Netlist or Verilog or VHDL source format
- Target technology – Xilinx, Altera, Lattice devices
- Test bench
- MATLAB, C, VHDL, Verilog simulation models available
- Detailed technical documentation.
Block Diagram of the 3GPP LTE FEC Encoder IP Core