Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications

Features

• Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
• Full Transaction Layer, Data Link Layer and Physical Layer
• Supports up to sixteen 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
• Available in 32-, 64-, 128-, 256- or 512-bit datapath widths for maximum flexibility
• 125 MHz, 250 MHz, 500 MHz, 1GHz operation
• Supports PIPE PHY 8-, 16-, 32-bit interface including variable clock and variable data
• Application interfaces include the Synopsys native interface or the optional Arm AMBA 4 AXI and 3 AXI application interface
• Optional embedded DMA controller with up to 8 read and 8 write channels for high throughput with minimal SoC resource overhead
• Configurable and efficient retry buffer design for low latency and area
• Supports automatic lane reversal and polarity inversion
• Supports L1 sub-states and power gating for low-power consumption
• RAS data protection providing ECC and/or Parity protection for internal busses and memories
• Advanced debug capabilities for error injection and statistical monitoring
• Ultra-low transmit and receive latency and high accessible bandwidth
• Validated with Synopsys and third-party PHYs and verification IP
• Supports up to 8 virtual channels and up to 8 traffic classes
• Directly supports up to 32 physical functions and up to 256 virtual functions using SR-IOV and ARI – Optional extension up to 64K Virtual Functions

Benefits

• Complete IP solution consists of digital controllers, PHYs, IP Prototyping Kits and verification IP
• Designed to meet all required features of the PCI Express 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s) and 1.1 (2.5 GT/s), and PIPE specifications
• Comprehensive suite of configurable controllers for Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode, and Multi-Port Switch applications
• Optimized for low power, small area and low latency
• PHYs include advanced built-in diagnostics, enabling at-speed production testing on low-cost digital tester
• Automotive Safety Integrity Level (ASIL) B Ready ISO 26262 certified controller and PHY IP
• Built-in applications in the verification IP accelerate testbench development

Deliverables

• The coreConsultant utility to guide designers through the installation configuration, architectural exploration, verification, and implementation of the IP
• Verilog RTL code
• Example PHY interfaces
• ASIC and FPGA synthesis scripts
• Verification environment
• Synopsys Verification IP for the PCI Express
• Documentation: release notes, installation/integration guide, application notes, user manual

Applications

• Enterprise computing, storage area networks, networking switches, and routers
• Wireless and mobile devices
• Industrial, automotive, and IoT
• Embedded systems and set-top boxes
• Graphics devices
• Desktops, laptops, workstations, and servers

Video Demo of the Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications

This demo video shows a complete end-to-end CCIX link operating at up to 25 Gb/s data rates, featuring the Synopsys CCIX PHY and controller IP. The demo highlights the advanced debug, error injection, and statistical analysis features as well as importance of setting the correct payload size for maximum throughput. The IP is CCIX 1.1 ready and can support operation at 32 GT/s.

• see the entire Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications datasheet
• get in contact with Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications Supplier