PCI Express 3.0, 2.0, 1.1 Controller IP Core with AMBA AXI User Interface

Features

• PCIe Interface
• Complies with the PCI Express Base 3.0 Specification, rev.3.1
• Supports Endpoint and rootport configuration
• Supports x16, x8, x4, x2, x1 at Gen3, Gen2, Gen1 speeds
• Implements one Virtual Channel
• Data protection (ECC, ECRC)
• Maximum payload size of up to 4KB
• Configurable Receive and Transmit Buffer size
• Supports SR-IOV, 6 BARs+ EPROM and Open interrupt interface, enabling SATA Express implementation
• Advanced features include: Advanced Error Reporting (AER), ECRC, MSI, MSI-X, ASPM and legacy power management, Lane Reversal, Hot Plug, peer-to-peer transactions, LTR
• PIPE 4.0 and PIE-8 compliant PHY interface
• 32-bit/250MHz in Gen3 mode on x1, x4, x8
• 16-bit mode supported only on x1, x4, x8 and x16
• Supported silicon:
• Process node/foundry agnostic digital controller
• Interoperable with PIPE 4.0 and PIE-8 compliant analog PHY IP
• Altera Stratix V, Xilinx Virtex-7
• AMBA AXI Interface
• Compliant to the AMBA AXI Specification v1.0 (AXI3) and AMBA AXI Specification v2.0 (AXI4)
• AXI-Lite Slave interface for IP configuration
• AXI-Lite Master interface to configure up to 8KB of user defined registers in AXI domain
• Multiple combination (configurable) of AXI Master, AXI Slave, AXI Stream interfaces
• Separate clock domains for each AXI interface
• Configurable data-path (64-bits/128-bits/256-bits)
• Data Engine and Address translation for PCIe-to-AXI and AXI-to-PCIe transfers
• Up to 8 DMA Engines for PCIe-to-AXI, AXI-to-PCIe, AXI-to-AXI transfers
• Up to 4GB (block) or infinite length transfers (packet)
• Up to 16 outstanding requests
• Support completion reordering
• Advanced Scatter-Gather DMA modes
• Reporting into Scatter Gather Descriptor
• Caching of descriptors to optimize throughput
• Up to 16 reconfigurable address translation tables for PCIe interface
• Up to 8 reconfigurable address translation tables per AXI4 slave interface

Benefits

• Engineered for both ASIC/SoC and FPGA implementations. Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL. Fully timing closed on leading edge FPGA from Altera and Xilinx.
• Advanced AMBA AXI interconnect enables heterogeneous SoC interfacing. Allows AXI3 and AXI4 peripherals to coexist and communicate efficiently through the interconnect interface.
• Fully configurable communication engine features programmable DMA and Address Translation Windows, allowing flexible and high-performance AXI-to-PCIe, PCIe-to-AXI, and AXI-to-AXI data transfers.
• Smart ordering rules management enables hazards and deadlocks prevention while ensuring optimized traffic flow.
• Configurable error detection and reporting enables application specific error management thus simplifying application software.
• Support for advanced Low Power states enables lower power consumption in energy-conscious applications
• Flexible PCIe interface configuration in endpoint and root port modes. Includes ECAM support for dynamic configuration of the entire PCIe hierarchy from the AXI domain.
• Provided with latency optimized Linux x64 PCIe device driver allowing immediate software development. Driver source code available for custom developments

Deliverables

• XpressRICH3-AXI IP
• Synthesizable Verilog RTL source code
• Simulation libraries for functional simulation
• Verilog RTL source code for synthesis/implementation
• PCI Express Bus Functional Model
• Simulation libraries
• Software design kit
• PCI Express Linux device driver (binary or source code)
• C API
• Reference design test executable and C++/Java source code
• Reference Design
• Synthesizable Verilog RTL source code
• Simulation environment and test scripts
• ASIC synthesis scripts
• Complete Documentation
• XpressRich3-AXI IP user's manual
• PCIe BFM user's manual
• SDK user's manual
• Getting Started manual

Block Diagram of the PCI Express 3.0, 2.0, 1.1 Controller IP Core with AMBA AXI User Interface

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