Amethyst provides a novel architecture of RS CODEC targeted for various communication standards.
The cores under RSFAMILY support different architecture offering optimization for different usage of the core.
- single clock design , standard cells
- up to 40Gbps throughput
- decoding capability of up to 2T
- configurable values of B,T,N
- Ease of integration - single clock design, standard cells, registered I/Os.
- Minimal Latency.
- minimal gatecount and RAM resource (possibility to have no RAM).
- RTL in Verilog (possible migration to VHDL)
- Testbench and test-vectors
- bit accurate Simulation model
- Warranty & Support Period - Customization if required
- For FPGA - netlist in encrypted format for evaluation