The Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPE) and the Turbo Product Decoder (ntTPD) blocks. The product code C is derived from two constituent codes, namely C1 and C2. The information data is encoded in two dimensions. Every row of C is a code of C2 and every column of C is a code of C1. The Configurable Turbo Product Codec supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening. Shortening is a way of providing more powerful codes by removing information bits from the code.
The Configurable Turbo Product Codec receives the information bits row by row from left to right and trans-mits the encoded bits in the same order. It consists of a row and column encoder. The row encoder encodes the data row-wise. The encoded data from the row encoder are stored in the encoded data memory. Concurrently, the information data are encoded column-wise by the column encoder and the column parity bits are stored in a separate memory.
The Configurable Turbo Product Codec receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The ntTPD core transmits the decoded bits in the same order. The implemented decoding algorithm computes the extrinsic information for every dimension by decoding words that are near the soft-input word. These words are called test patterns and their number can be programmed.
- Programmable data block size by adjusting codeword dimensions, i.e. number of rows and number of columns.
- Supports shortening by adjusting number of rows and columns to be eliminated in order to create a shortened code.
- Programmable number of soft bits in the input data.
- 2’s complement arithmetic data format.
- Supports extended Hamming or single parity constituent codes.
- Supports (64,57), (32,26), (16,11) or (8,4) extended Hamming constituent codes.
- Supports (64,63), (32,31), (16,15) or (8,7) single parity constituent codes.
- Programmable number of algorithmic iterations.
- Supports user selectable synchronous reset.
- Fixed encoder and decoder latency.
- Supports ASIC and FPGA implementation technologies.
- Single edge, fully synchronous design.
- Area efficient design.
- Silicon proven in Xilinx FPGA technologies for a variety of applications.
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configura-tion files.
- C++ model.
- Comprehensive technical documentation.
- Technical support.