Upgraded PUF-based Crypto Coprocessor (Compliant with TLS 1.3 / FIPS 186-5)
Configurable UART with FIFO, hardware and software flow control
The hardware flow control significantly reduces software overhead and increases system efficiency, by automatically controlled serial data flow using the RTS output and CTS input signals.
Software flow control automatically monitors data flow, by using programmable Xon/Xoff characters.The UART includes a programmable baud rate generator, that can divide the timing reference clock input by a divisor between 1 and (216-1).
The separate BAUD CLK line allow to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency.
D16752 includes fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow. Our efficient Core is a technology independent design, that can be implemented in a variety of process technologies.
The configuration capability allows you to enable or disable during the Synthesis process the Modem Control Logic and the FIFO's Control Logic and change the FIFO size. So, in applications with area limitation and where the UART works only in a 16450 mode, disabling the Modem Control and FIFO's allow to save about 50% of logic resources.
The Core is perfect for applications, where the UART core and a microcontroller are clocked by the same clock signal and implemented inside the same ASIC or FPGA chip. Nevertheless, our solution is designed for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks the D16752, the CPU interface core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system.
The D16752 UART Core can operate as dual channel, as well as single channel UART.
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