The Trilinear Technologies AVP-35 Content Adaptive Deinterlacer core provides advanced algorithms and high quality results for demanding video applications. The AVP-35 implements content adaptive processing in both the temporal and spatial domains. Temporal processing includes multiple level motion detection while spatial processing analyzes image details in order to enhance both large and small details. Additional non-linear filtering techniques further improve image quality.
At the heart of the AVP-35 core is a high precision motion detection unit which is capable of classifying movement between fields into multiple categories. These differing classes of motion are used by the reconstruction algorithms to provide the highest level of image quality possible. In addition to temporal analysis, the AVP-35 processing algorithms utilize spatial content analysis to further modify the progressive reconstruction process to preserve large and small image details. Additional non-linear processing algorithms are also applied during the reconstruction process resulting in high levels of image quality.
The AVP-35 is delivered as either a technology specific firm core or a technology independent soft core and may be implemented on both FPGA and ASIC platforms. The Trilinear Technologies’ development process allows for the migration if soft cores from FPGA to ASIC for prototyping and production solutions with no core modifications. The AVP-35 core offers an optimal solution for both technologies without the typical limitations of performance in ASIC form and area in FPGA form. This flexibility is achieved through a state of the art internal architecture and best in class design practices.
The AVP-35 core ships with a comprehensive ‘C’ reference driver, a fully documented API and a sample video player application. The core is available for evaluation on the Trilinear Technologies’ Viper Development platform. This FPGA based reference system provides a complete environment for core evaluation as well as early software development.
- Real time, content adaptive interlaced to progressive format conversion
- Zero CPU overhead after initial configuration
- Programmable reconstruction control from host
- Core Details
- Core clock at 2x input clock
- Integrated cadence detection
- Multi-level motion detection
- Linear and non-linear filtering
- AMBA APB 3 Slave Interface
- 24, 30, 36-bit pixel support
- Reference Software
- ‘C’ source code included
- Complete device driver
- Real time video player
- Fully documented API
- FPGA Development Platform
- 32-bit MCU based system
- Real time video input and output
- Includes the AVP-35 CA Deinterlacer, DDR memory system and display controller
- DVI digital output
- HDL source files for the function design
- HDL source files for block level and top level testing
- Functional specification
- Timing constraints summary document
- Generic SRAM simulation models
- C Reference Driver
- Sample video player application
Block Diagram of the Content Adaptive Deinterlacer IP Core