The M_CAN is a CAN IP module that can be realized as a stand-alone device, as part of an ASIC, or as an FPGA. It performs communication according to ISO 11898-1:2015. Additional transceiver hardware is required for connection to the physical layer.
The message storage is intended to be a single- or dual-ported Message RAM outside of the module. It is connected to the M_CAN via the Generic Master Interface. Depending on the chosen integration, multiple M_CAN controllers can share the same Message RAM.
All functions concerning the handling of messages are implemented by the Rx Handler and the Tx Handler. The Rx Handler manages message acceptance filtering, the transfer of received messages from the CAN Core to the Message RAM and provides receive message status information. The Tx Handler is responsible for the transfer of transmit messages from the Message RAM to the CAN Core and provides transmit status information.
Acceptance filtering is implemented by a combination of up to 128 filter elements whereas each one can be configured as a range, as a bit mask, or as a dedicated ID filter.
The M_CAN module is delivered with a 32-bit CPU interface. For FPGAs an exemplary interface converter is provided (e.g. to an Avalon interface). They can easily be replaced by a user-defined module interface.