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Controller IP for CXL
XpressLINK™ is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation. The XpressLINK Controller IP leverages PLDA's silicon proven XpressRICH Controller for PCIe 5.0 architecture for the CXL.io path, and adds the CXL.cache and CXL.mem paths specific to CXL. XpressLINK exposes PLDA native Tx/Rx user interface for CXL.io traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic. XpressLINK also complies with the Intel PHY Interface for PCI Express (PIPE) specification version 5.x. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including CXL device type, PIPE interface configuration, buffer sizes and latency, low power support, SR-IOV parameters, etc. for optimal throughput, latency, size and power. XpressLINK is extensively verified using commercial as well as homegrown VIP and testsuites, and has been integrated with a number of PCIe 5.0 PHY IP.
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Block Diagram of the Controller IP for CXL IP Core
Video Demo of the Controller IP for CXL IP Core
In this video, we demonstrate the PLDA XpressLINK Controller IP for CXL 2.0 and the CXL.mem protocol used to access Host-managed Device Memory, or HDM. This demonstration is performed using Intel’s Pre-Production Xeon CPU as a host, connected to an FPGA board, instantiating PLDA’s CXL Controller and CXL.mem test design.