64x8 Bits OTP (One-Time Programmable) IP, X-FAB 0.18μm XH018 Modular Mixed Signal
The Lattice CORDIC IP is configurable and several functions can be implemented in the IP core: Rotation, Translation, Sin and Cos, Arctan. Two architecture configurations are available for the arithmetic unit: Parallel, with single cycle data throughput, and Word-serial, with multiple cycles throughput. The input data, output data widths and iterative number are configurable over a wide range. The IP core uses full internal precision while allowing variable output precision with several choices for rounding.
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Block Diagram of the CORDIC IP Core
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