The CR16CP uses the industry-standard AMBA™ AHB bus system, providing full 32-bit data memory space, and supporting Nexus 5001 compliant on-chip debug capabilities.
The CR16P architecture was specifically designed for embedded systems and delivers excellent code density, low power consumption, and small die area with the ability to tightly integrate on-chip acceleration, I/O and memory functions. The architecture has firmly established itself by filling a previously unmet need—those applications that require significant embedded performance, but cannot afford the size and cost overhead of full 32-bit RISC implementations. The architecture is enhanced with valuable controller features, like a variable length instruction set and direct bit manipulation to make it even more effective for embedded applications. CR16 implementations have been proven in many NXP standard parts.
- Cache support: Up to 8 KB instruction cache
- 3-stage pipeline: Instruction Fetch (IF), Instruction Decode (ID), Execution (EX)
- Variable instruction length (16, 32, or 48 bits)
- Backward compatible with National Semiconductor CR16A and CR16B products
- Supervisor and user modes for operating system (OS) support
- 16x16 multiply (configurable as single cycle or multicycle)
- Low power achieved through compact design and dynamic clock gating
- Double word arithmetic & load/store instructions
- Verilog source code
- Integration Testbench and Test-suite
- Comprehensive Documentation
- Scripts for simulation and synthesis with support for common EDA tools
Block Diagram of the CR16CP Processor (70014) IP Core