The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90.
Basic core is small (6,500 gates) and uses an external 256-bit entropy seed to generate 16 bytes (128 bits) of random data at a time (128 bits of security strength). Versions of the core are available supporting higher security strengths (192 and 256 bits), larger amounts of generated bits (up to 219), and different internal datapath widths for size/performance tradeoff. The core includes the AES1 core.
The design is fully synchronous and available in both source and netlist form. Test bench uses vectors in plain text format.
PRNG1 core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.