Scalable, On-Die Voltage Regulation for High Current Applications
CSI2 TX; Camera Serial Interface, MIPI Compliant
This IP is efficient and functionally verified and well tested design for the Camera Serial Interface – 2 (CSI – 2 version 1.1) and D – PHY version 1.1 and can be immediately used in SoC designs in need of the CSI Interface.
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Block Diagram of the CSI2 TX; Camera Serial Interface, MIPI Compliant
CSI2 IP
- MIPI CSI-2 Controller Core V2
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- MIPI CSI DSI Controller - CPHY CSI-2 Transmitter v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP in TSMC 40ULP
- MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm