CSI2 – TX is part of HCL’s MIPI® compliant offerings. The CSI2 Transmitter IP supports Pixel Interface on the camera sensor side and the DPHY is supported through the PPF interface. The IP is designed to be operate as single or multiple data lanes (up to 4) based on the sensor bandwidth required in the camera module. It offers APB Bus interface by default for communication with MPU. It can be customized quickly if needed, for other leading industry standard bus interface to MPU such as Avalon, AXI4 – Lite and AHB.
This IP is efficient and functionally verified and well tested design for the Camera Serial Interface – 2 (CSI – 2 version 1.1) and D – PHY version 1.1 and can be immediately used in SoC designs in need of the CSI Interface.
- Supports up to 4-Data lanes
- Supports up to 4-virtual channels
- The Data lanes can be programmed to operate either at 1 or 2 or 3 or 4 lanes
- Each Data lane supports up to 1.5Gbps at High Speed mode and up to 10 Mbps at Low power mode
- Supports data formats (YUV420-8/10bits, YUV422-8/10bits, RGB888, RGB565, RAW8, RAW10, Generic 8/10-bits and User defined Byte based formats)
- Supports APB interface for register programming
- Supports ECC and CRC Generation
- Supports High speed data, Ultra Low power (Escape mode) control and Low power data modes of operations
- Source Code – Verilog HDL
- Verification Environment
- Synthesis Scripts
- Timing Constraints
- User Manual
Block Diagram of the CSI2 TX; Camera Serial Interface, MIPI Compliant