The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices requiting high performance, heterogeneous computing for data-intensive workloads. The Synopsys DesignWare® CXL 2.0 Integrity and Data Encryption (IDE) Security IP Module provides confidentiality, integrity and replay protection for FLITs in the case of CXL.cache and CXL.mem protocols and for Transaction Layer Packets (TLP) in the case of CXL.io. The Security Module is compliant with the IDE specification as defined for CXL 2.0 which also references PCI Express IDE specification for the CXL.io protocol. The DesignWare CXL 2.0 IDE Security Module integrates seamlessly with the Synopsys DesignWare CXL controllers to accelerate SoC integration.
DesignWare CXL 2.0 IDE Security Module
The DesignWare CXL 2.0 IDE Security Module supports full-duplex for .cache/.mem and .io Rx and Tx directions. It provides efficient encryption/ decryption and authentication of FLITs and TLPs, based on optimized low latency AES-GCM cryptographic cores, that are specially developed to meet an optimal area vs. performance implementation.