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CXL (Compute Express Link) Dual Mode Controller
Highly Configurable, Technology Independent, System Validated.
Mobiveil's COMPEX controller is a highly configurable design targeted for high speed low latency CPU interconnect that enables a high speed, efficient performance between the CXL compliant CPU and platform enhancements and work load accelerators.
COMPEX is part of Mobiveil's CXL family of IP solutions which includes supports for Device only (COMPEX-DEV), Host only (COMPEX-HOST) and Dual Mode (COMPEX-DM) designs
The controllers simple configurable and layered architecture is independent of application logic, PHY designs, Implementation tools and target process
Mobiveil's COMPEX controller is a highly configurable design targeted for high speed low latency CPU interconnect that enables a high speed, efficient performance between the CXL compliant CPU and platform enhancements and work load accelerators.
COMPEX is part of Mobiveil's CXL family of IP solutions which includes supports for Device only (COMPEX-DEV), Host only (COMPEX-HOST) and Dual Mode (COMPEX-DM) designs
The controllers simple configurable and layered architecture is independent of application logic, PHY designs, Implementation tools and target process
Features
- Compliant with CXL Specification version 1.1 and PCIe Base Specification 5.0 (32 Gbps per lane)
- Complaint with PIPE 5.x interface
- Supports X16, X8, X4, X2 and X1 lane widths
- Supports 512, 256 and 128 Data path widths
- Supports PCI Express Alternate Protocol
- Supports Dual Mode of operation (Host and Device)
- Supports CXL.io, CXL.cache, and CXL.mem protocols
- Supports Type1, Type 2 and Type 3 CXL device types
- Supports all requests and Response type packets for CXL.io, CXL.cache and CXL.mem protocols
- Independent packet oriented User Interface for each protocol (CXL.io, CXL.cache and CXL.mem protocols)
- Supports viral CXL containment feature
- Supports SR-IOV. ATS, FLR and AER for CXL.io
- Completely handles ordering rules for CXL.io, CXL.cache and CXL.mem in TX and RX directions
- Implements flow control logic in both directions
- Supports high;y efficient flit-packing algorithm on TX path
- Supports Data poisoning
Benefits
- The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption and silicon foot print
- Technology independent- Available for ASIC, FPGA and Structured ASIC
- Easy integration to an SOC
- Fully verified with 3rd party VIP
Deliverables
- Data sheet
- RTL/Encrypted RTL
- Test bench/environment
- Test cases
- FPGA Prototype
Applications
- Artificial Intelligence
- Machine Learning
- Data storage
- Could infrastructure
View CXL (Compute Express Link) Dual Mode Controller full description to...
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