Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications
The Cadence® Controller IP for CXL provides the logic required to integrate an endpoint (EP) controller into any system on chip (SoC). The Controller IP has been extensively tested using Cadence Verification IP for PCIe/CXL and is built on the underlying PCIe Controller that has been tested on the Cadence Palladium® series of verification computing platforms. Cadence offers a comprehensive IP solution that is in volume production and successfully implemented in dozens of applications. Client applications access the controller through the industry-standard Arm® AMBA® 5.0 AXI interface or through a native Cadence interface, the Host Adaptation Layer—Streaming (HLS). The Controller IP is engineered to quickly and easily integrate into any CXL Cache Coherent SoC and connect seamlessly to a PIPE5.2-compliant PCIe PHY.