Arasan Chip Systems announces the immediate availability its MIPI D-PHY IP supporting speeds of
upto 2.5 gbps for TSMC 22nm SoC designs. The MIPI D-PHY IP is seamlessly integrated with
Arasan own CSI Tx, CSI Rx, DSI Tx and DSI Rx as part of its Total MIPI Imaging and Display IP
Solution. Compared to 28nm high-performance compact (28HPC) technology, 22ULP provides 10% area reduction
with more than 30% speed gain or more than 30% power reduction.
Arasan's D-PHY IP Compliant to MIPI D-PHY Spec reuses multiple blocks
from our silicon proven 28nm technology to reduce risk while the design is optimized to
leverage the TSMC 22nm technology node for reduction in area and power compared to our
The Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification.
It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols.
It is a universal PHY that can be configured as a transmitter, receiver or transceiver.
The D-PHY consists of an analog front end to generate and receive the electrical level signals,
and a digital back end to control the I/O functions.
The Arasan D-PHY provides a point to point connection between master and slave or host and device
that comply with a relevant MIPI® standard. A typical configuration consists of a clock lane
and 1-4 data lanes. The master/host is primarily the source of data and the slave/device is usually
the sink of data. The D-PHY lanes can be configured for unidirectional or bidirectional lane
operation, originating at the master and terminating at the slave.
It can be configured to operate as a master or as a slave.
The D-PHY link supports a high speed (HS) mode for fast data traffic and a low power (LP) mode
for control transactions. In HS mode, the low swing differential signal is able to support
The Arasan D-PHY Analog Transceiver IP core implements the PPI interface recommended by the MIPI®
working groups to easily interface to the required protocols.