The S3TXBIASDSS28LPP circuit has been designed to reduce time to market, risk and cost in the development of analog front-ends. A range of supporting IP blocks such as PLL's, clock buffers, amplifiers, Analog-to- Digital (ADC) and Digital-to-Analog (DAC) converters are also available.
The S3TXBIASDSS28LPP has been implemented on 28nm LPP process. However it is readily portable to any similar manufacturing process. Any activity of this nature can be fully supported.
The Bandgap circuit is a standard implementation using an array of matched PNP transistors to generate the PTAT (Proportional To Absolute Temperature) term.
The Bandgap voltage is used to create accurate bias currents. These bias currents are generated with an external resistor and whereby this resistor can adjust the output full-scale current.
- 28nm Samsung LPP Process, 6 Metals Used
- 1.8V and 1.0V Supplies
- Accurate 1.0V Bandgap Reference
- Tolerance of Bandgap Voltage < ±3.5%
- Current consumption
- Active mode:0.79mA
- Power down: 0.2uA
- Compact Die Area:0.024mm2
- The S3TXBIASDSS28LPP is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- Reference Generation
- Current & Voltage Regulation
- General Mixed Signal Products
Block Diagram of the DAC Bias Block IP Core