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Data Compression
Helion currently offer a very high performance implementation in hardware for the LZRW3 lossless compression algorithm. A choice of separate compression and expansion engines, or a combined compressor / decompressor is available, each capable of processing at gigabit rates in typical ASIC or FPGA targets.
These high performance cores are available in versions for use in ASIC, Altera and Xilinx FPGA, and in common with all Helion IP cores they have been designed with each technology firmly in mind to yield the very best and most efficient results.
These high performance cores are available in versions for use in ASIC, Altera and Xilinx FPGA, and in common with all Helion IP cores they have been designed with each technology firmly in mind to yield the very best and most efficient results.
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Data Compression IP
- Image Data Fixed-length Compression/Decompression IP
- CCSDS 122.0-B-1 Encoder - Lossless and Lossy Image Data Compression with up to 16 bits Pixel Dynamic Range
- GZIP/ZLIB/Deflate Data Compression Core
- Image Data Fixed-length Compression/Decompression
- 1/8 Image data Fixed-length Compression/De-compression RTL Core
- High Throughput and Low Latency Data Compression Engine