The S3DCBIASC40LP is a DC biasing circuit has been designed to provide a 0.55V (Typical) stable DC Biasing voltage to reduce time to market, risk and cost in the development of Analog Front-Ends and Regulators.
A range of supporting IP blocks such as PLL, PGA, Analog-to-Digital (ADC) and Digital-to-Analog (DAC) converters are also available.
The S3DCBIASC40LP has been implemented on a standard 40nm logic process. However it is readily portable to any similar manufacturing process. Any activity of this nature can be fully supported.
- UMC 40nm CMOS 3.3V/1.2V Process
- No Analog Options
- 1.2V Supply
- Generated DC Bias Voltage of 0.55V ±1%
- Tunable Biasing Resistor Range from 40KOhm to 1.2MOhm
- Power Consumption
- Active Mode: 0.6 uW (RES_SEL<4:0> = '00000' )
- Power Down: 0.01 uW
- Fast Start Option
- Compact Die Area:0.0026mm2
- The S3DCBIASC40LP is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (Verilog)
- Integration Support
Block Diagram of the DC Bias Block IP Core