The Cadence Denali High-Speed DDR PHY IP supports DDR4/DDR3/DDR3L, provides low latency, and enables up to 3200Mbps throughput and bandwidth necessary for today s mobile, enterprise, and consumer applications, while balancing power consumption. The PHY IP is silicon proven and designed for ease of integration and faster time-to-market.
The PHY IP is engineered for quick and easy integration into system-on-chips (SoC), and is verified with the Denali DDR Controller IP as part of a complete memory subsystem solution. The PHY IP provides a DFI-compliant memory controller interface.The PHY IP is validated with multiple hardware platforms for reduced risk and is designed to be interoperable with various supplier memory chips.
The PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of interface, Denali memory interface, analog, and systems and peripherals IP.