This memory controller supports DDR3/4 SDRAM. DDR3/4 memory controller is a high-speed interface used for data read/write between internal engine and outside SDRAM bus, and transfers the internal signal to meet the SDRAM specification.
The DDR3/4 memory controller includes several Sub-Arbiters , Main-Arbiter and Controller module.
Sub-Arbiter supports 4 masters. Sub-Arbiter would be placed in partition or in memory controller. Main-Arbiter supports 16 masters. The memory arbiter will do arbitration one all the masters’ (internal engines) request and send those request to DDR (Double Data Rate) controller.
The DDR (Double Data Rate) controller will convert the internal request to DRAM chip protocol for data read/write. The DDR controller also implements the DRAM refresh, DRAM dynamic power down, DRAM Scramble and DRAM Private Usage functions