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DDR and LPDDR 3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
DesignWare® DDR Memory Interface IP is a family of complete system-level IP solutions for system-on-chips (SoCs) requiring an interface to one or more of the broad range of high-performance DDR5, DDR4, DDR3/3L, DDR2, LPDDR5, LPDDR4/4X, LPDDR3, LPDDR2, and LPDDR SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power, and enhanced signaling features, the complete DesignWare DDR Memory Interface IP solution includes a choice of scalable digital controllers, an integrated hard macro PHY (including I/Os), and verification IP.
The two types of DDR digital controller IP, DesignWare DDR Memory Controller IP and DesignWare DDR Protocol Controller IP, feature a DFI-compliant interface with low latency, and high bandwidth. They offer the flexibility of clock frequency ratios between PHY and controller to allow for easier timing closure in slower processes, and lower latency in faster technologies.
The two types of DDR digital controller IP, DesignWare DDR Memory Controller IP and DesignWare DDR Protocol Controller IP, feature a DFI-compliant interface with low latency, and high bandwidth. They offer the flexibility of clock frequency ratios between PHY and controller to allow for easier timing closure in slower processes, and lower latency in faster technologies.
Features
- #1 supplier of DDR interface IP (IPnest 2017)
- Comprehensive DDR IP solution includes protocol and memory controllers and PHY IP
- Products support various combinations of DDR5, DDR4, DDR3/3L, DDR2, LPDDR5, LPDDR4/4X, LPDDR3, LPDDR2, and LPDDR standards
- Each solution supports at least two generations of DDR standards (for example, DDR5 and DDR4)
Benefits
- Four memory controller offerings: uMCTL2: multi-ported memory controller supporting JEDEC standard DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3, and LPDDR4, and LPDDR4X SDRAM and DIMM modules
- uPCTL2: Single-ported version of uMCTL2 with no internal scheduler; DDR5/4 controller: multi-ported memory controller supporting JEDEC standard DDR5, DDR4 SDRAMs and DIMM modules
- LPDDR5/4/4X controller: multi-ported memory controller supporting JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
- High-bandwidth design with up to 64 CAM entries for Reads and 64 CAM entries for Writes, and latency as low as 6 clock cycles
- Best in class performance with unique features such as QoS based scheduling and dual-channel support
- Offers several RAS features, such as Sideband ECC, Inline ECC, Command/Address Parity, etc., where supported by the DRAM protocol
- In-line ECC function provides error correction in systems that cannot use a sideband ECC
- LPDDR5/4/4X controller and uMCTL2 have an automotive license option, which has been designed with automotive safety features and includes ISO 26262 Work Products
Deliverables
- Executable .run installation file
- Databook (PDF)
- Release notes (PDF)
- coreConsultant/coreAssembler tools to generate RTL
Applications
- Mobile multimedia
- Digital home and office
- Wireless connectivity
- Automotive
- Artificial Intelligence/machine learning/ deep learning
- Data centers (networking and storage)
- Smartphones and tablets
- Ultraportable laptops/ultrabooks
Video Demo of the DDR and LPDDR 3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
SDRAMs such as DDR, LPDDR, and HBM offer unique advantages for automotive, artificial intelligence (AI), cloud, and mobile applications. However, the selected memory solution impacts the performance, power, and area requirements of SoCs, making it important to choose the right memory technology and interface IP for the target design. Meet your specific design targets by using Synopsys’ high-performance, silicon-proven DDR memory interface IP solutions compliant with the latest JEDEC standards.
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