DDR/DDR2 SDRAM Controller MACO Core
This proven DDR/DDR2 core is optimized utilizing MACO ASIC gates in the LatticeSCM devices, resulting in fast, small cores that utilize the latest architecture to its fullest.
Note the RLDRAM IP Core is implemented using both MACO ASIC gates and soft logic in the FPGA array. Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.
Software Requirements
* ispLEVER version 7.1 or later
* MACO design kit
* MACO license file
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Block Diagram of the DDR/DDR2 SDRAM Controller MACO Core
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