LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
DDR SDRAM Controller - Pipelined
Hardware Demo
A hardware demonstration bitstream for this IP core is available for use with the LatticeEC Advanced Evaluation Board. The bitstream, and a complete description of its operation is available for download by clicking the "Design Files" link in the resource box on this page.
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Block Diagram of the DDR SDRAM Controller - Pipelined IP Core
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