English
You are here:
DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process
DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process
View DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process full description to...
- see the entire DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process datasheet
- get in contact with DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process Supplier
Interface Solution IP
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- Interlaken Protocol IP (High Speed Chip-To-Chip Interface)
- Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC with AMBA AXI User Interface
- Common Public Radio Interface (CPRI) v.7.0 IPC
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- Common Public Radio Interface (CPRI) v.6.1 IPC