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DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration - SMIC 40nm LL
DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration in SMIC 40nm LL
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DDR2 IP
- ONFI 3.2 NV-DDR2 PHY in GDSII
- SSTL with bi-directional I/O’s, Vref, and ODT for DDR2 memory (1.8 V)
- DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP
- 1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process
- Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
- UMC 65nm LP/RVT LowK Logic Process DDR2/DDR1/MDDR Combo I/O using 2.5V I/O devices_x000D_ _x000D_