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DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration - SMIC 40nm LL
DDR2/DDR3/DDR3L/LPDDR/LPDDR2/LPDDR3 6 in one combo IO with auto calibration in SMIC 40nm LL
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DDR2 IP
- ONFI 3.2 NV-DDR2 PHY in GDSII
- SSTL with bi-directional I/O’s, Vref, and ODT for DDR2 memory (1.8 V)
- DDR2/DDR3/DDR3L/LPDDR2 I/O Buffer - TSMC 40 CLN40LP
- DDR2/DDR1/MDDR Combo Command/Address Block ; UMC 65nm LP/RVT LowK Logic Process
- Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical version
- LPDDR3/2 DDR3/2 Combo PHY TSMC 130G