Adaptive Clock Generation Module for DVFS and Droop Response
DDR2 & DDR3 Fault Tolerant Memory Controller
On the memory side, it presents a DFI interface for connection to an on-chip physical layer (PHY) that manages the low-level timing and data recovery and then provides the I/O buffers. Towards the system-on-chip, it presents the memory through an AMBA AHB slave interface.
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