4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
DDR2 SDRAM Controller - Pipelined
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Block Diagram of the DDR2 SDRAM Controller - Pipelined IP Core
![DDR2 SDRAM Controller - Pipelined Block Diagam](http://www.design-reuse.com/sip/blockdiagram/9453/9-main-DDR2-SDRAM-Controller-Pipelined.png)
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