The Altera® DDR and DDR2 SDRAM High-Performance Controller MegaCore® functions provide simplified interfaces to industry-standard DDR SDRAM and DDR2 SDRAM. The MegaCore functions work in conjunction with the Altera ALTMEMPHY physical interface megafunction. The controllers offer a half-rate interface and a full-rate interface to the customer application logic. For exact device support, please refer to the user guide.
The MegaWizard Plug-In Manager generates an example design, instantiates a phase-locked loop (PLL), an example driver, your DDR or DDR2 SDRAM controller custom variation, and an optional DLL (for Stratix® series FPGAs only). The example design is a fully functional design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals. Figure 1 shows a system-level diagram including the example design that the DDR or DDR2 SDRAM Controller MegaCore functions create for you.
- SOPC Builder Ready: Yes
- Qsys Compliant: Yes