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DDR3/2 PHY in Samsung (45nm, 32nm)
Synopsys DesignWare® DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3 and DDR2 SDRAM memories. The DDR3/2 PHY IP supports the entire range of DDR3 SDRAM speeds, from DDR3-800 through DDR3-2133, with backward compatibility provided for DDR2-667 through DDR2-1066 devices. The PHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR3/2 PHY is constructed from the following libraries of components: the application specific SSTL I/O library, a single address/command macro block and multiple byte wide data macro blocks instantiated as many times as required to accommodate the memory channel width. Finally, the DesignWare DDR3/2 PHY includes a PHY Utility Block (PUB) that is supplied as soft IP. The PUB contains the circuitry to calibrate and maintain the calibration of the DDR3/2 PHY’s delay lines, provide voltage and temperature based correction to the I/O drive impedance and ODT settings, the PHY configuration registers, testability circuitry such as the at-speed loopback controller and the DFI 2.1 interface.
A key component of the DesignWare DDR3/2 PHY is the extensive in system data training/calibration capability in order to maximize the overall timing budget and improve system reliability. The DesignWare DDR3/2 PHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling.
A key component of the DesignWare DDR3/2 PHY is the extensive in system data training/calibration capability in order to maximize the overall timing budget and improve system reliability. The DesignWare DDR3/2 PHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling.
Features
- Compatible with JEDEC standard DDR2/DDR3/DDR3L SDRAMs
- Operating range of 667 to 1066Mbsp in DDR2 mode
- Operating range of 667 to 2133Mbsp in DDR3 mode y Maximum data rate is process dependent
- DFI 2.1 compliant interface to the memory controller
- Small PHY area – e.g., <1.3mm2 for a 16-bit DDR3 PHY in 40nm (including I/Os)
- Low power – e.g., <350mW for a 16-bit PHY with DDR3 SDRAMs
- Configurable external memory channel widths in 8-bit increments from 8 to 72-bits
- Permits operating with a narrower memory channel than the implemented memory channel width (for example, an SoC supporting a 32-bit memory channel can optionally operate with a 16-bit channel)
- Programmable I/O output drive strength and ODT impedance with dynamic PVT compensation
- Delivery of product as hardened IP components allows precise control of timing critical delay and skew paths
- Includes embedded timing circuits necessary to generate the clocks and strobes for the DRAM interface and meet the narrow timing specifications of DDR3 SDRAMs
- Multiple memory-rank support, up to four ranks
- Flexible I/O ring design permitting exact match to the end system requirements (e.g., straight PHY or can go around a corner, flexible power to signal ratio, number of core power supply pins, number of ranks supported, channel width, number of address pins, etc.)
- Supports DDR3 write leveling
Benefits
- Supports JEDEC standard DDR3, DDR3L (1.35V DDR3) and DDR2 SDRAMs
- High performance DDR PHY supporting data rates from 667 to 2133Mbps
- GDSII based “hard” PHY avoids timing closure problems common with “soft” RTL-based DDR PHYs
- Designed for rapid integration with Synopsys Protocol or Memory controller for a complete DDR interface solution
- Includes application specific DDR I/Os including programmable drive strength and ODT
- DFI 2.1 compliant controller interface
Deliverables
- Verilog behavioral model
- Synopsys lib timing model
- LEF layout abstract views & GDSII layout cells
- Spice netlists for layout versus schematic (LVS) checks
- Detailed datasheets, implementation guide, IBIS models
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