The performance leading INNOSILICON DDR PHY supports DDR5/LPDDR5 DDR4/LPDDR4/DDR3/LPDDR3/DDR2/LPDDR2/DDR at speeds up to 6400Mb/s and in any bus width.
Silicon proven in mass production and test chips, the PHY combines low power consumption with its small size. This compact form factor is translated into low I/O pin count, simplifying both package substrate and PCB, while potentially allowing for board level routing with only 2 layers.
Leveraging a choice of DFI V2.0/V2.1/V3.0/V3.1/V4.0/ standards, the PHY can be integrated with memory controller from our own or major compatible 3rd parties. It is fully register controlled via an APB and the production testing is simplified through high-speed BIST, loopback modes, and boundary scan.
With a self-contained yet modular design, the PHY contains the I/Os, ESD, a timing synch module DLLs and can be expanded to a virtually unlimited bus width. The Optional components include customer specific bus widths, integrated PLLs, custom pinouts, and the Innosilicon memory controller which supports AHB/AXI and FIFO interfaces. We provide custom DDR solutions to meet your needs while handling whatever level of integration support as you required.