DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)
The DDR IP is silicon proven. The PHY is optimized for high performance, low latency, low area, low power, ease of integration and faster time-to-market.
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Block Diagram of the DDR3/ DDR2 Combo PHY IP - 1866Mbps (Silicon Proven in UMC 40LP)
DDR3 PHY IP IP
- DDR3 PHY - GLOBALFOUNDRIES 12nm
- DDR3/4 and LPDDR2/3/4/4x Combo PHY&MAC
- DDR3/DDR4 IP solution with high performance and low power
- Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
- DDR3/LPDDR23 PHY - 55LL
- DDR3/LPDDR23 PHY - 65LL