The IPX-DDR2 core is a DDR2 memory controller for Xilinx devices running up to 266 MHz and with bus width of up to 64 bits. This intoPIX core reduces the number of logic resources and improves the latency of row accesses. The DDR2 Memory controller guarantees efficient DDR2 access to the JPEG 2000 IP-cores and is fully compatible with all the families of intoPIX JPEG 2000 IP-cores.
The user interface is a bus of up to 256-bit width running at up to 133 MHz. The maximum peak rate transfer is 64 x 2 x 266 ~= 34 Gbit/s. The physical bus width is selectable between 8, 16, 32 and 64 bits, and the user interface is also selectable between 32, 64, 128 or 256 bit.
- Slices: Less than 1500 slices for a 32-bit wide physical data-bus; user
- data bus of 128-bit
- RAMBs: Non
- DSPs: Non
- Frequency: 266MHz (533 Mbps per data bit)
- Configurable data memory width
- Continuous random data accesses within the same row
- Reduced footprint. Area is linear with respect to the data memory width
- High operating frequency supported
- Efficient integration with memory arbiter cores, including IPX-MA (Memory Arbiter)