DDR3 / DDR4 / LPDDR3 / LPDDR4 / LPDDR5 Memory Controller
OMC is a very small & highly configurable DDR memory controller. It provides very high performance through advanced memory controller design based on proprietary out-of-order scheduling algorithm and high speed implementation technique. Demand for more DRAM bandwidth is getting stronger than ever in a quest to improving user experiences (e.g. higher image resolution). Given the limited amount of physically available DRAM bandwidth, highly efficient memory controller IP is becoming a very critical issue everywhere. With our OMC, SoCs can save significant amount of area & power consumption and meet next generation SoC’s DRAM bandwidth requirements.
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Block Diagram of the DDR3 / DDR4 / LPDDR3 / LPDDR4 / LPDDR5 Memory Controller
