The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3 memory Controller (MC) and the DDR3 memory devices compliant with JESD79-3 specification. The DDR3 PHY IP provides the Industry standard DDR PHY Interface (DFI) bus at the local side to interface with the Memory Controller. The DFI protocol defines the signals, signal relationships, and timing parameters required to transfer control information and data to and from the DDDR3 devices over the DFI bus.
The DDR3 PHY IP reduces the effort required to integrate any DDR3 memory controller with Lattice FPGA’s DDR3 primitives and thereby enables the user to implement only the logical portion of the memory controller in the user design. The Lattice’s DDR3 PHY IP contains all the logics required for Memory device initialization procedure, Write leveling, Read data capture and Read data de-skew that are dependent on FPGA DDR IO primitives.